A dual damascene process is a technique used to form interconnects in an insulator layer. Typically, the insulator layer is patterned to form vias and trenches. The vias and trenches are filled with metal to form conducting wires and via plugs. The conventional dual damascene process is described in Licata et al., “Dual Damascene AI Wiring for 256 M Dram”, VCIM Conference 1995, pgs-596-602. For example, a via hole is first etched, followed by the etching of a trench overlying the via opening. Disadvantages of the dual damascene process include the unevenness of the resist coating and the reflectivity from the substrate which distorts the resist image. In addition, the photoresist inside the via hole is removed prior to etching the trench so that no protection layer is present for the subsequent trench etch step. Thus, there is damage to the layer underlying within the via hole.
U.S. Pat. No. 6,365,529 to Hussein et al., reveals a method for forming dual damascene copper interconnects using a reactive ion etching of a sacrificial layer that fills the previously formed contact hole. U.S. Pat. No. 6,350,681B to Chen et al., reveals a dual damascene process that uses a chemical mechanical polishing process to remove the barrier layer material outside the via holes. U.S. Pat. No. 6,268,283B1 to Huang discloses a transparent spun on cap layer underneath the resist to prevent damage by the developer to the dielectric underlayers. U.S. Pat. No. 6,013,581 to Wu et al., discloses a dual damascene process that includes a plasma treatment of the exposed dielectric layer below the opening before the openings are filled with conductive material. U.S. Pat. No. 6,057,239 to Wang et al. discloses a damascene process that includes a plasma treatment of the exposes a portion of the oxide layer by using reactive ion etchback of the antireflective layer that filled the contact hole. The oxide layer is then wet etched to form the wiring trough.
Some papers have been published that reflect on the issues of conventional dual damascene and these include using a BARC (bottom antireflective layer) layer such as in Ding et al., “Optimization of Bottom Antireflective Coating Materials for Dual Damascene Process”, SPIE Proceedings, 3999,910-918 (1999), Pollentier et al., “Dual Damascene back-end Patterning using 248 nm and 193 nm Lithography,” Interface 2000, pgs 265-284 (2000) and Gadson, Solid State Technology, pg. 77 (2001).
The dual damascene process using a single layer of photoresist with no BARC suffers from reflectivity issues or line width dependency on thickness of the resist. Attempts to solve this problem include using a BARC under the resist. FIG. 1A illustrates a conventional dual damascene process using a BARC layer. Semiconductor device structures, not shown, may be formed in and on semiconductor substrate 10. One of these structures is to be contacted by a dual damascene interconnect. An etch stop layer 12 is deposited over the surface of the substrate.
A first thick insulator layer 14 is deposited over the etch stop layer 12. A second insulator layer 16 may be deposited over the insulator layer 14. 16 may be a hard mask layer. A layer of photoresist 20 is patterned to form a via hole opening as shown. IF a hard mask is used, the via pattern is transferred to the hard mask 16 and the photoresist 20 is removed. The insulator layer is etched to form a via opening 25 as shown in FIG. 1B.
Now, as shown in FIG. 1C, a layer of organic bottom antireflective layer (BARC) 30 is coated over the substrate and filling the via opening. A second photoresist layer 30 is coated over the substrate, as illustrated in FIG. 1D. The photoresist is patterned as shown in FIG. 1E to form a trench opening 35. Using the remaining resist as an etch mask and the BARC as a protection sublayer for etch stop 12, the insulating layers are etched to form the dual damascene opening as shown in FIG. 1F. The resist and BARC are stripped and the dual damascene opening is filled with metal 38 as shown in FIG. 1G.
The BARC process of the prior art can introduce “fence-like” etching resides 29. The fence-like structures are believed to arise if the BARC thickness on the sidewall of the via opening, as shown in FIG. 1C, is too thick or if the BARC is not recessed below the trench stop layer. This is becaused the BARC etch rate is too low in an oxide or low dielectric constant (k) material etch process. Another issue that may arise during imaging is that materials may diffuse from the insulating layer 14 into the resist 25, causing so-called poisoning of the resist. This can cause a positive resist to form an insoluble interfacial layer to residues in the image of the via hole pattern.